I just share a link which might be useful, but maybe you already know it.

Here's an open source tool for formal verification and SysML modeling called TTool, to check a software design always respects some constraints and safety guarantees you set, even before writing the code.
https://ttool.telecom-paris.fr/
Helps you detect deadlocks and make sure some error states are impossible to reach, or at least they're always handled in the safest possible way.

Said that, welcome to HPR!